A large number of power electronics applications now require the generation of an intermediate dc voltage stage. Taking the example of a variable speed motor, shown in FIG. 1, the motor will derive a power supply from a standard ac mains supply 10 at the local voltage and frequency. The mains supply is fed to a mains filter 15, which serves to protect the equipment from any spurious signals on the supply as well as to prevent unwanted signals generated by the equipment from being propagated over the supply. The ‘cleaned’ supply is then converted to dc by a dc link stage 20. The conversion to dc includes a bridge rectifier D1-D4 and some form of circuitry to produce a more even, dc-like, output from the rectified signal, such as a capacitor. In this example, the dc link stage includes a boost Active Power Factor Correction stage (boost APFC stage) 25 which will be described more fully below.
Another example of the use of an intermediate dc stage is in ac-to-dc-to-dc converters which are used for dc power supplies. In these types of power supply a mains ac supply is first converted to dc before being converted to dc at the required voltage.
Typically, passive forms of power conversion which include an intermediate dc stage have a disadvantage in that they distort the shape of the voltage and current waveforms drawn from the mains supply. Electromagnetic Compatibility Standards (EMC), such as those set out in British Standard EN 61000-3-2 (1995) and in the EMC Directive (89/336/EEC), define an acceptable level for the harmonic content in the current which electrical equipment draws from a mains ac supply, as well as an acceptable level of voltage distortion. These standards place constraints on how power conversion can be carried out. In addition, the power factor is of concern since this will determine the rating of components such as the mains cable and whether the local mains supply system will be adequate.
The way in which the dc link is implemented varies according to the required output power of the system. For a low power load, a dc output can be achieved very simply by placing a capacitor Cdc across the output of the bridge rectifier, in parallel with the load. In order to maintain a highly regulated dc voltage, the dc side capacitor Cdc must have a high capacity. The large capacitor Cdc causes the input current to have a low power factor, and current is only drawn from the mains supply when the magnitude of the mains input voltage (Vac) is greater than the dc voltage (Vdc). The input current resembles a series of spaced-apart peaks, which causes a significant low frequency harmonic content. It is this harmonic content that limits this approach to low power systems only, since for higher power loads the harmonic content would breach the levels defined by the EMC regulations or lead to an unacceptably low power factor.
Various techniques have been developed to improve the quality of the input current. Additional components can be added to the input filter stage, or the well known ‘valley fill’ circuit can be used. The valley fill circuit improves the input current shape by splitting the dc link capacitor into two. For the standard bridge rectifier, current is drawn from the mains supply when the magnitude of the mains input voltage (Vac) is greater than the dc voltage (Vdc). However, for the valley fill circuit, current is drawn when the magnitude of the mains supply is greater than half of the dc voltage (Vdc/2). This means that current is taken from the mains for a longer period than that of the standard bridge rectifier, resulting in an improved power factor.
Due to the harmonic limitations of the above schemes, actively controlled input rectifiers are often used. The most common of these is the boost APFC stage shown in FIG. 1.
Two control loops—a voltage control loop and a current control loop—define the switching action of power transistor TR1. The voltage control loop maintains the dc link voltage (Vdc) at the required level, and this is achieved by adjusting the amplitude of the current control loop's current reference. The current control loop ensures the input current follows the reference defined by the voltage control loop. This multi-loop control structure dictates that one loop must be dominant. The general convention is that the current control loop dominates. This has the effect that dc voltage regulation (particularly during transient events) is limited, due to the limited performance of the slave loop. Generally, increasing the value of the dc link capacitance (Cdc) compensates for this limitation.
FIGS. 2 and 3 show both the start-up transient and the steady state performance of the converter. Initially (0<t<0.005 seconds), the converter is uncontrolled (the action of the boost stage is irrelevant if Vdc<|Vac|). Once the condition Vdc>|Vac| is achieved, the boost APFC stage actively controls the input current to be substantially sinusoidal, with very good power factor. The high frequency superimposed on the main 50 Hz component is due to the switching action of the boost converter and is directly related to the switching frequency of TR1. The selected switching frequency for the converter must be sufficiently greater than the harmonic limits imposed by the EMC standards.